Title :
Architectural and compiler support for the extraction and execution of coarse-grain parallelism
Author :
Abdelrahman, Tarek S.
Author_Institution :
Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Abstract :
This paper presents a summary of our work on the multi-level computing architecture (MLCA) project. The goal of this project is to provide novel architectural and compiler support for the extraction and execution of coarse-grain parallelism in multimedia applications on parallel-embedded systems. We first give an overview of the architecture and its novel features. We then describe the need for and the details of its compiler support. We present an experimental evaluation of a prototype MLCA system, including the architecture and the compiler. The results indicate that the MLCA is a promising architecture for supporting coarse-grain parallelism on parallel embedded systems.
Keywords :
parallel processing; parallelising compilers; MLCA; architectural support; coarse-grain parallelism; compiler support; multilevel computing architecture; parallel-embedded systems; Computer science; Counting circuits; Educational institutions; Frequency; History; Performance loss; Pollution; Runtime; System performance; Very large scale integration;
Conference_Titel :
Communications, Computers and Signal Processing, 2009. PacRim 2009. IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
978-1-4244-4560-8
Electronic_ISBN :
978-1-4244-4561-5
DOI :
10.1109/PACRIM.2009.5291236
