Feasibility Study of Composite Dielectric Tunnel Barriers for Flash Memory

A novel optimization methodology is developed for deriving the minimum operational voltage of a composite tunnel dielectric stack for flash memory. The methodology accounts for normal flash operation constraints: retention, read and program disturb, and reveals that the higher J-Vgs nonlinearity of these stacks can result in up to 40% voltage reduction. The symmetric stack is found to be more efficient than asymmetric in reducing voltage. The optimum materials along with their thickness are also identified. Experiments confirm the nonlinearity in J-Vg_s using HfSiON_x, a high- kappa which for the first time is used in the context of Flash memory.