CASh: a novel "Clock As Shield" design methodology for noise immune precharge-evaluate logic

In gigascale integrated circuits (GSI), interconnects are expected to play a more dominant role in circuit performance than transistor cells. The circuit performance is affected by signal integrity as cross-talk becomes more significant with the sealing of feature sizes. Many attempts have been made to improve noise immunity, but all require the sacrifice of speed as a tradeoff, especially in dynamic circuits. Avoiding noise problems while maintaining the desired speed would involve increased wire spacing or extensive shielding, both of which are unfavorable due to demands for high density and a relatively higher cost of wires in current process technologies. We propose a novel methodology in which clock lines are used as shielding wires to reduce cross-talk effects in domino circuits, thereby minimizing the possibility of functional failures. In addition, this method provides another benefit: a small buffer size is required for driving a long interconnect for iso-noise immunity. Since clock lines, which are always required in domino circuits, are used to shield signal lines, speed penalty and area overhead which are drawbacks of previous work can be avoided. This design methodology CASh (Clock As Shielding) demonstrates the superiority over conventional methods. HSPICE simulations on a 2-input domino AND gate and 4 and 8-bit full adders designed in CASh show higher noise immunity over conventional design.