Breaking the bottleneck of sequential decoding for high-speed digital communication

An efficient ASIC architecture for the sequential stack decoding (SSD) algorithm used for channel coding is presented. It is different from the maximal likelihood (ML) Viterbi decoder (VD), mainly in the search for the correct memory path. Due to the dedicated memory organization, the storage space and required hardware can be reduced while the decoding efficiency remains almost the same. The proposed architecture results from step by step design of the I/O interface, high-level memory management, dedicated data paths, and controller. The ordering of these steps is important in optimizing the final solution. In addition, the construction of this hardware organization can be made by using the available hardware building blocks