Color permutation: an iterative algorithm for memory packing

It is predicted that 70% of silicon real-estate will be occupied by memories in future system-on-chips. The minimization of on-chip memory hence becomes increasingly important for cost, performance and energy consumption. In this paper, we present a reasonably fast algorithm based on iterative improvement, which packs a large number of memory blocks into a minimum-size address space. The efficiency of the algorithm is achieved by two new techniques. First, in order to evaluate each solution in linear time, we propose a new algorithm based on the acyclic orientation of the memory conflict graph. Second, we propose a novel representation of the solution which effectively compresses the potentially infinite solution space to a finite value of n!, where n is the number of vertices in the memory conflict graph. Furthermore, if a near-optimal solution is satisfactory, this value can be dramatically reduced to /spl chi/!, where /spl chi/! is the chromatic number of the memory conflict graph. Experiments show that consistent improvement over scalar method by 30% can be achieved.