Title :
Modeling of Multi-layer Nanocrystal Memory
Author :
Hou, Tuo-Hung ; Lee, Chungho ; Kan, Edwin C.
Author_Institution :
Cornell Univ., Ithaca
Abstract :
In this paper, we show that the same compact physical model is applicable to the double-layer nanocrystal (DL NC) memory. To further optimize memory performance, design criteria of the size ratio between two layers of NCs and the configuration with multi-layer NCs are explicitly examined.
Keywords :
circuit optimisation; dielectric devices; dielectric thin films; integrated circuit design; integrated circuit modelling; integrated memory circuits; multilayers; nanoelectronics; nanostructured materials; design criteria; double-layer nanocrystal memory; memory performance optimisation; multilayer nanocrystal memory modeling; physical model; trap-free dielectrics; Channel bank filters; Design optimization; Dielectrics; Electrostatics; Fabrication; Gold; Nanocrystals; Solid modeling; Thickness control; Tunneling;
Conference_Titel :
Device Research Conference, 2007 65th Annual
Conference_Location :
Notre Dame, IN
Print_ISBN :
978-1-4244-1101-6
Electronic_ISBN :
1548-3770
DOI :
10.1109/DRC.2007.4373727
