DocumentCode
1959873
Title
Simulated annealing: a fast heuristic for some generic layout problems
Author
Lam, J. ; Delosne, J.-M.
Author_Institution
Yale Univ., New Haven, CT, USA
fYear
1988
fDate
7-10 Nov. 1988
Firstpage
510
Lastpage
513
Abstract
It is shown that simulated annealing, with a properly designed annealing schedule and move-generation strategy, achieves significant speedups for high-quality solutions when compared with tailored heuristics on two well-studied problems: the traveling-salesman problem and the graph-partition problem. Efficient heuristics can be applied to power and ground routing for the traveling-salesman problem and to min-cut placement and logic partitioning for the graph-partition problem.<>
Keywords
VLSI; circuit layout CAD; optimisation; graph-partition; ground routing; logic partitioning; min-cut placement; move-generation strategy; power routing; simulated annealing; traveling-salesman problem; Cities and towns; Computational modeling; Computer science; Computer simulation; Logic; Optimization methods; Routing; Simulated annealing; Testing; Traveling salesman problems;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-0869-2
Type
conf
DOI
10.1109/ICCAD.1988.122560
Filename
122560
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