Power-delay modeling of dynamic CMOS gates for circuit optimization

Author

Rossello, J.L. ; Segura, J.

Author_Institution

Phys. Dept., Balearic Islands Univ., Palma de Mallorca, Spain

fYear

2001

fDate

4-8 Nov. 2001

Firstpage

494

Lastpage

499

Abstract

We present an accurate analytical expression to compute power and delay of domino CMOS circuits from a detailed description of internal capacitor switching and discharging currents. The expression obtained accounts for the main effects in complex sub-micron gates like velocity saturation effects, body effect, device sizes and coupling capacitors. The energy-delay product is also evaluated and analyzed. Results are compared to HSPICE simulations (level 50) for a 0.18 /spl mu/m CMOS technology.

Keywords

CMOS digital integrated circuits; SPICE; VLSI; capacitors; circuit optimisation; circuit simulation; delays; electric current; integrated circuit design; integrated circuit modelling; 0.18 micron; CMOS technology; HSPICE simulations; body effect; circuit optimization; coupling capacitors; device sizes; domino CMOS circuits; dynamic CMOS gates; energy-delay product; internal capacitor discharging currents; internal capacitor switching currents; power-delay modeling; velocity saturation effects; CMOS logic circuits; Capacitance; Capacitors; Circuit optimization; Clocks; Delay; Energy consumption; MOSFETs; Power dissipation; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on

Conference_Location

San Jose, CA, USA

ISSN

1092-3152

Print_ISBN

0-7803-7247-6

Type

conf

DOI

10.1109/ICCAD.2001.968689

Filename

968689