• DocumentCode
    1960001
  • Title

    Interconnection delay and clock cycle selection in high level synthesis

  • Author

    Mecha, H. ; Fernández, M.

  • Author_Institution
    Departimento Inf. y Autom., Universidad Complutense de Madrid, Spain
  • fYear
    1997
  • fDate
    4-7 Jan 1997
  • Firstpage
    504
  • Lastpage
    505
  • Abstract
    This paper presents a method to estimate the delay of interconnections. It uses a simple model based exclusively on point to point interconnections. The method has a very low complexity so it can be used during the clock cycle selection in a High Level Synthesis process. In this way it is possible to settle securely the right electrical behavior of the final circuit
  • Keywords
    clocks; computational complexity; delays; high level synthesis; integrated circuit interconnections; integrated circuit modelling; clock cycle selection; electrical behavior; high level synthesis; interconnection delay; low complexity; physical model; point to point interconnections; Capacitance; Clocks; Delay effects; Delay estimation; Frequency estimation; High level synthesis; Integrated circuit interconnections; Libraries; Voltage; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1997. Proceedings., Tenth International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-7755-4
  • Type

    conf

  • DOI
    10.1109/ICVD.1997.568184
  • Filename
    568184
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1960001