Title :
Interconnection delay and clock cycle selection in high level synthesis
Author :
Mecha, H. ; Fernández, M.
Author_Institution :
Departimento Inf. y Autom., Universidad Complutense de Madrid, Spain
Abstract :
This paper presents a method to estimate the delay of interconnections. It uses a simple model based exclusively on point to point interconnections. The method has a very low complexity so it can be used during the clock cycle selection in a High Level Synthesis process. In this way it is possible to settle securely the right electrical behavior of the final circuit
Keywords :
clocks; computational complexity; delays; high level synthesis; integrated circuit interconnections; integrated circuit modelling; clock cycle selection; electrical behavior; high level synthesis; interconnection delay; low complexity; physical model; point to point interconnections; Capacitance; Clocks; Delay effects; Delay estimation; Frequency estimation; High level synthesis; Integrated circuit interconnections; Libraries; Voltage; Wire;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568184
