Computer-aided design of high-speed lattice wave digital filter integrated circuits

Author

Liu, Lynette ; Yoshino, Tomonobu ; Sprouse, Steven ; Jain, Rajeev

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

1991

fDate

14-17 April 1991

Firstpage

1229

Abstract

A silicon compiler for generating IIR filter integrated circuits based on the lattice wave digital filter structure is presented. A novel architecture has been developed to minimize the chip area while achieving a high throughput. A fifth-order filter synthesized with the compiler measures 4.17 mm/sup 2/ and has an estimated sample rate of at least 60 MHz in 0.8 mu m BiCMOS gate-array technology. This represents an order of magnitude improvement over the lattice wave digital filter compiler.<>

Keywords

BIMOS integrated circuits; circuit CAD; circuit layout CAD; digital filters; digital integrated circuits; 0.8 micron; 60 MHz; BiCMOS gate-array; CAD; IIR filter integrated circuits; chip area minimisation; computer aided design; digital IC; fifth-order filter; high-speed lattice wave digital filter; sample rate; silicon compiler; Computer architecture; Design automation; Digital filters; Digital integrated circuits; IIR filters; Integrated circuit synthesis; Lattices; Semiconductor device measurement; Silicon compiler; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont., Canada

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150615

Filename

150615