Title :
A design flow for optimal circuit design using resource and timing estimation
Author :
Gharibian, Farnaz ; Kent, Kenneth B.
Author_Institution :
Fac. of Comput. Sci., Univ. of New Brunswick, Fredericton, NB, Canada
Abstract :
In this paper, we study and investigate resource estimation methods that are used in circuit design for field programmable gate arrays (FPGAs). These methods usually estimate the amount of resources to be consumed by a hardware design before circuit synthesis takes place. The purpose of this study is to analyze the suitability of an estimation method for a design flow. A framework is also proposed to help the optimization process of the design. This framework automatically optimizes the design by finding potential parallelism in the design and applies it while considering the available resource and time constraints.
Keywords :
circuit optimisation; field programmable gate arrays; integrated circuit design; FPGA; circuit synthesis; field programmable gate arrays; hardware design; optimal circuit design; optimization; resource estimation; timing estimation; Circuit synthesis; Delay estimation; Design optimization; Field programmable gate arrays; Hardware design languages; High level languages; Process design; Programmable logic arrays; Programming profession; Timing;
Conference_Titel :
Communications, Computers and Signal Processing, 2009. PacRim 2009. IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
978-1-4244-4560-8
Electronic_ISBN :
978-1-4244-4561-5
DOI :
10.1109/PACRIM.2009.5291369
