DocumentCode
1960683
Title
Single-pass redundancy-addition-and-removal
Author
Chih-Wei Chang ; Marek-Sadowska, M.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear
2001
fDate
4-8 Nov. 2001
Firstpage
606
Lastpage
609
Abstract
Redundancy-addition-and-removal is a rewiring technique which for a given target wire w/sub t/ finds a redundant alternative wire w/sub a/. Addition of w/sub a/ makes w/sub t/ redundant and hence removable without changing the overall circuit functionality. Incremental logic restructuring based on this technique has been used in many applications. However, the search for valid alternative wires requires trial-and-error redundancy testing of a potentially large set of candidate Wires. We study the fundamental theory behind this technique and propose a new reasoning scheme which directly identifies alternative wires without performing trial-and-error tests. Experimental results show up to 15 times speedup in comparison to the best techniques in literature.
Keywords
combinational circuits; logic CAD; logic gates; logic testing; redundancy; timing; wiring; candidate wires; combinational logic restructuring technique; incremental logic restructuring; logic gates; logic synthesis; overall circuit functionality; reasoning scheme; redundancy-addition-and-removal; rewiring technique; single-pass technique; speedup; target wire; timing estimation; trial-and-error redundancy testing; Circuit testing; Engines; Field programmable gate arrays; Filters; Logic gates; Performance evaluation; Redundancy; Routing; Timing; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-7247-6
Type
conf
DOI
10.1109/ICCAD.2001.968723
Filename
968723
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