A simulation methodology for software energy evaluation

We describe a comprehensive simulation methodology and tool for evaluation of software energy for the pipelined DLX processor. Energy models for each module of DLX are built and the energy is evaluated during run time execution. The input to the simulator are the instructions of the program and the simulator estimates energy of each micro-instruction using the energy models. Our simulator allows exploration of energy by allowing architecture modification, experimentation with different software techniques (compilation optimizations, algorithm evaluation) and also allows simultaneous interplay of both hardware and software techniques. The usefulness of this simulator is demonstrated by evaluating certain compilation optimizations (loop unrolling, software pipelining, recursion elimination etc.) and algorithms