Very high voltage integration in SOI based on a new floating channel technology

Summary form only given. For smart power devices, SOI HV device integration is an attractive technology. It allows integration of MOS controlled bipolar power transistors or thyristors and bidirectional AC power switches, with dielectric isolation between control and high potential regions. Si direct bonding was expected to be a successful VHV SOI technology, as >1 kV isolation to the handle wafer was expected for 2 /spl mu/m bonding oxide thickness. A major drawback, however, arises from the back-gate effect due to electric field extension into the SOI at high potentials, e.g. high anode voltage. An inversion channel which would shield the Si from high fields is extracted by the lateral electric field, leading to punchthrough or avalanche generation at the anode, trying to restore the channel and thus generating high blocking currents. Relatively thick SOI layers (/spl ap/20 /spl mu/m) are thus necessary to obtain devices with 500-600 V blocking capability for 220 V operation, and larger thicknesses are necessary for bidirectional AC switches. Trench isolation becomes very expensive and extension to 1 kV devices for integrated power electronic transistor drivers is not possible. We propose a new technique based on dielectric micro-barriers which enable formation of floating channel segments, based on the consideration that partial inversion channel formation shields the Si from high electric fields, when channel extraction can be prohibited, and that closely spaced channel segments have the same electrostatic effect as a continuous channel. By varying segment width, a quasicontinuous channel charge density variation can be obtained.