The use of inverse layout trees for hierarchical design verification

The authors present the inverse layout tree as a means of performing fully hierarchical design verification without any restrictions on subcell overlaps. This provides a fast and general method of marking design rule errors or extracted devices at the correct hierarchical level. The inverse layout tree for each element is built up as layout data is processed from the bottom up. When layout processing is completed one can go through the layout again and use the inverse layout trees to determine the most appropriate cell for each element. New elements formed as layout from different cells overlap can now be placed at the lowest level of hierarchy where they always appear instead of being indiscriminately incorporated in the parent cell. The method preserves the original hierarchy to the greatest possible extent. The method has been implemented in the corner-based design-rule checker and circuit extractor, Corny. As an important example it is shown that logical DIFF (ANDNOT) operations between layers can be performed fully hierarchically.<>