Core Mapping into an Irregular Network on Chip - Features Extraction System for Automatic Speech Recognition Case Study

Author

Dziurzanski, P. ; Maka, Tomasz

Author_Institution

Fac. of Comput. Sci. & Inf. Technol., West Pomeranian Univ. of Technol., Szczecin, Poland

fYear

2013

fDate

Feb. 27 2013-March 1 2013

Firstpage

494

Lastpage

498

Abstract

In this paper, we propose a mapping scheme of IP cores into irregular Network on Chips using an example module dedicated to features extraction for automatic speech recognition system. We estimated the core sizes for various frame sizes and overlappings, and then tried to place cores communicating heavily close to each other, we test a number of widths in the 2D Rectangular Strip Packing problem. The obtained result range allows us to pick a solution that is beneficial both in terms of area and transfers between the system cores.

Keywords

feature extraction; logic circuits; network-on-chip; speech recognition; 2D rectangular strip packing problem; IP cores; automatic speech recognition; core mapping; core size estimation; feature extraction system; frame sizes; irregular network on chip; Algorithm design and analysis; Computer architecture; Feature extraction; Speech; Speech processing; Strips; Vectors; IP core mapping; Network on Chip; features extraction; strip packaging problem;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel, Distributed and Network-Based Processing (PDP), 2013 21st Euromicro International Conference on

Conference_Location

Belfast

ISSN

1066-6192

Print_ISBN

978-1-4673-5321-2

Electronic_ISBN

1066-6192

Type

conf

DOI

10.1109/PDP.2013.79

Filename

6498595