Fully-depleted 0.25 /spl mu/m SOI devices for low power RF mixed analog-digital circuits

Fully-depleted (FD) SOI devices have interesting characteristics for low power applications because of their low subthreshold swing and their low source/drain capacitances compared to bulk devices. Furthermore, floating body effects are much reduced compared with partially-depleted devices (PD), so that they are among the best candidates for mixed analog-digital circuits in mobile wireless communication systems. However, the main concern is their manufacture with an ultra-thin silicon film (/spl sim/40 nm), which is required to obtain complete film depletion and good control of short channel effects (SCE) and barrier lowering (DIBL) at the same time, in order to obtain optimized 0.25 /spl mu/m gate length devices. To avoid a drastic increase of source/drain resistance, different solutions have already been proposed for the source/drain, including selective epitaxy, W CVD or a TiSi/sub 2/ salicide process with a very thin sputter thickness. As the TiSi/sub 2/ process is critical on ultra-thin silicon, NiSi has also been tried successfully. Nevertheless, all of these solutions must use a new nonconventional process. The recessed-channel structure (Faynot et al, IEEE Electron Dev. Lett. vol. 15, no. 5, 1994; Chan et al. ibid, vol. 15, no. 1, 1994), on the contrary, needs only a conventional LOCOS to thin the silicon locally. We demonstrate in this paper that the electrical characteristics do not suffer from the nonself-aligned process between gate and thicker source/drain regions if source/drain ion implantations are well optimized.