A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC

Author

Beigne, Edith ; Miro-Panades, Ivan ; Thonnart, Yvain ; Alacoque, Laurent ; Vivet, Pascal ; Lesecq, Suzanne ; Puschini, Diego ; Thabet, Farhat ; Tain, Benoit ; Benchehida, K. ; Engels, S. ; Wilson, Richard ; Fuin, D.

Author_Institution

MINATEC, CEA, Grenoble, France

fYear

2013

fDate

16-20 Sept. 2013

Firstpage

57

Lastpage

60

Abstract

In order to optimize global energy efficiency in the context of dynamic Process-Voltage-Temperature variations in advanced nodes, a fine-grain Adaptive Voltage and Frequency Scaling architecture is proposed and implemented on a 32 nm GALS Multi-Processor SoC. Each Processing Element is an independent Voltage-Frequency island and shows up to 18.2% energy gains due to local adaptability. Compared to a worst case approach, our proposal also allows a frequency boosting around 25% for a total area overhead of 10% including local frequency/voltage actuators, sensors and digital controller.

Keywords

system-on-chip; GALS MPSoC; GALS multiprocessor SoC; digital controller; dynamic process-voltage-temperature variations; fine grain variation-aware dynamic Vdd-hopping AVFS architecture; fine-grain adaptive voltage-frequency scaling architecture; frequency boosting; global energy efficiency; globally asynchronous-locally synchronous MPSoC; independent voltage-frequency island; local frequency-voltage actuators; processing element; sensors; size 32 nm; Actuators; Clocks; Frequency control; Process control; Sensors; Timing; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2013 Proceedings of the

Conference_Location

Bucharest

ISSN

1930-8833

Print_ISBN

978-1-4799-0643-7

Type

conf

DOI

10.1109/ESSCIRC.2013.6649071

Filename

6649071