The study of reducing branch penalty by hardware

Pipeline technique is the major method to increase the performance of single processor, but when processing branch instructions, we must wait the result of branch to decide the next instruction; we call the waiting time “Branch Penalty”, which will influence the performance of pipeline processor. Branch target buffer is an important method to resolve the branch penalty, but branch penalty occurs when the prediction incorrect. In this paper, we propose a method to reduce the branch penalty when the prediction falls into an error on branch target buffer