System approach for low 1/f noise, high IP2 dynamic range CMOS mixer design

This paper presents system approach considerations for an RF Downconversion mixer design with low 1/f noise, improved second-order intermodulation distortion and low local oscillator (LO) signal reradiation. The intended application is for direct-conversion and ultra low intermediate frequency (IF) receiver systems. The mixer, implemented in a standard 3.3 V 0.35 μm CMOS process, achieves a second-order input intercept point (IIP2) of at least +80 dBm. The design utilizes a 25% duty cycle square wave LO control signal with single to differential output sampling mixer architecture to enhance DC offset rejection and improve mixer IIP2 performance. Local oscillator signal waveforms are optimized to minimize undesirable LO signal leakage and LO self-mixing. External and intrinsic noises in the proposed sampling mixer are analyzed using time and frequency domain methods. Analytically calculated and measured results are compared. In addition, direct-conversion receiver system architecture advantages, inherent problems analysis and second-order intermodulation background are given.