Title :
A high speed compact priority encoder
Author_Institution :
Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA
Abstract :
A high-speed compact priority encoder for high-density parallel operations is developed. A simple and highly efficient CMOS technique is implemented for the construction of the priority resolution (PR) modules. The technique is based on a staircase array structure, and it is shown that the use of such an array reduces the hardware and causes parallel operations in the modules within the same level. This, in turn, reduces the overall time delay in the device by a large amount. A selective use of the precharge/predischarge scheme also provides a considerable reduction in the time response of the PR modules
Keywords :
CMOS integrated circuits; encoding; logic arrays; CMOS technique; compact priority encoder; high-density parallel operations; precharge/predischarge scheme; priority resolution; staircase array structure; time delay; time response; Application software; CMOS technology; Circuits; Delay effects; Digital arithmetic; Hardware; Logic devices; Modular construction; Signal resolution; Time factors;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101828
