Title :
Time interval measurements using integrated tapped CMOS delay lines
Author :
Rahkonen, Timo ; Kostamovaara, Juha ; Säynäjäkangas, Seppo
Author_Institution :
Dept. of Electr. Eng., Oulu Univ., Finland
Abstract :
An integrated seven bit time-to-digital converter (TDC) based on tapped CMOS delay lines was designed and tested. Its single-shot resolution is about 700 ps, and the ultimate resolution of averaged results is 50-100 ps. The linearity and gain of the converter are markedly dependent on the layout and ambient conditions
Keywords :
CMOS integrated circuits; analogue-digital conversion; delay lines; time measurement; ambient conditions; averaged results; gain; integrated tapped CMOS delay lines; layout; linearity; single-shot resolution; time-to-digital converter; Clocks; Counting circuits; Delay lines; Linearity; Semiconductor device measurement; Signal design; Testing; Time measurement; Timing jitter; Tin;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101829
