The Realization and Optimization of Secure Hash Algorithm (SHA-1) Based on LEON2 Coprocessor

This paper describes the design flow of Secure Hash Algorithm (SHA-1) which based on LEON2 coprocessor, and provides a series of optimized design proposals. First, modify the interface of the coprocessor to increase the bandwidth; second, make use of the principle of data-driven to expand the instruction set; next, through optimizing the critical path design, dynamic generating the variables Wt (0lestles79) and optimizing the output to increase the speed, decrease the scale and lower the dynamic power; finally, modify the software package binutils-2.16.1 to support the expanded assembler instructions. This design is described in VHDL, and has passed Xilinx Virtex-5 FPGA testing verifies. Because of the characteristics of low cost and high performance, this design is available for various kinds of security domains.