• DocumentCode
    1962098
  • Title

    Kaolin: A system-level AADL tool for FPGA design reuse, upgrade and migration

  • Author

    Blouin, Dominique ; Ochoa-Ruiz, Gilberto ; Eustache, Yvan ; Diguet, Jean-Philippe

  • Author_Institution
    Syst. Anal. & Modeling Group, Hasso-Plattner Inst., Potsdam, Germany
  • fYear
    2015
  • fDate
    15-18 June 2015
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    Nowadays, the development, maintenance and evolution of products based on FPGAs remains a difficult and time consuming task, especially in today´s stringent and fast-paced markets. Designers need to master technology-specific implementation details, which often vary across FPGA models, tool versions and vendors, thus making it difficult to port code from one target device to another. To address these problems, we present the Kaolin model-based development process and tool. Kaolin users design their systems at the functional level, whilst the execution platform-specific details are automatically generated according to the selected FPGA platform model. Additionally, legacy HDL code can be imported thanks to state-of-the-art bi-directional model transformations, so that existing systems can be retargeted to other FPGA platforms. The advantages of Kaolin are demonstrated via an industrial acoustic recorder case study, which has been automatically imported into Kaolin and retargeted to a different FPGA platform with improved performances.
  • Keywords
    field programmable gate arrays; hardware description languages; logic design; FPGA design reuse; FPGA models; FPGA platforms; Kaolin model-based development process; execution platform-specific details; fast-paced markets; functional level; industrial acoustic recorder case study; legacy HDL code; state-of-the-art bidirectional model transformations; system-level AADL tool; technology-specific implementation details; tool versions; Field programmable gate arrays; Hardware; Libraries; Object oriented modeling; Ports (Computers); Solid modeling; Unified modeling language; AADL; EDA and CAD Tools; FPGA; MBE; MDD;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Adaptive Hardware and Systems (AHS), 2015 NASA/ESA Conference on
  • Conference_Location
    Montreal, QC
  • Type

    conf

  • DOI
    10.1109/AHS.2015.7231166
  • Filename
    7231166