Title :
IEEE International Conference on Computer-Aided Design, ICCAD-88. Digest of Technical Papers [Front Cover]
Abstract :
Presents the front cover of the conference proceedings.
Keywords :
circuit CAD; circuit analysis computing; circuit layout CAD; logic CAD; logic testing; network topology; CAD; CMOS matrix layout; PLAs; ROM-based CMOS cell generation; VLSI; algorithmic fault simulation techniques; analog circuit synthesis; analog layout; analog layout parallel simulation techniques; automatic test pattern generation; channel routing; circuit simulation; circuit verification; device simulation; fault simulation; finite-state-machine synthesis; floorplannng; global routing; high-level synthesis; high-performance computers; layout data structures; logic; multilevel simulation; multilevel synthesis; optimization; parametric issues; performance issues; placement; power-bus current estimation; processor architecture; scheduling; self-test; statistical design techniques; switch-level simulation; switchbox routing; technology mapping; test compaction; testable design techniques; timing simulators; topological routing; verification; yield enhancement;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122572
