RISP design with most optimal configuration overhead for VLIW based architectures

In this research paper an alternative design for reconfigurable instruction set processor (RISP) has been proposed with the capability of the most optimal configuration overhead for Very Long Instruction Word (VLIW) based architectures. This processor supports the demand-driven modification of its instruction set during the program execution. The processor has been integrated with the high speed partially reconfigurable field programmable gate array (FPGA) cores as its reconfigurable functional units (RFUs) in place of ALUs and it treats instructions as removable modules which can be paged in and paged out through the partial reconfigurations according to the requirements of the application being under execution. Instructions occupy the FPGA resources only when needed and FPGA resources can be released and reused at run-time on a fly for other kind of instructions belonging to the same or the different applications without affecting those who are currently under execution on the FPGA platform. RISPs are the next generation of processors which can adapt their instruction sets through a reconfiguration in their hardware according to the requirements of the applications being under execution on them. In this way the processor adapts its instruction set for the hardware design which is the most suitable for the application being executing on it, during the process of its execution and hence it accelerates the performance. RISPs are the programmable processors which contain the reconfigurable logic in one or more of their functional units. The hardware design of such a kind of processor can be categorized into two main tasks: The first task is to design the reconfigurable logic itself and the second task is to design the communication interface of reconfigurable logic with the remaining modules of the processor.