Title :
A simulated annealing approach for automatic extraction of device and material parameters of MOS with SiO2/high-K gate stacks
Author :
Li, Fei ; Mudanai, Sivahmar P. ; Fan, Yang-Yu ; Zhao, Wei ; Register, Leonard F. ; Banerjee, Sanjay K.
Author_Institution :
Microelectron. Res. Center, Texas Univ., Austin, TX, USA
fDate :
30 June-2 July 2003
Abstract :
A program with ability to extract device and material parameters of MOS capacitors with nanometer scale effective oxide thicknesses (EOTs) SiO2/high-K gate dielectrics from experimental gate capacitance (C-V) and gate leakage current (I-V) with high accuracy in a few minutes is demonstrated. Simulated annealing algorithm was used as the optimisation approach. The device parameters such as EOTs, surface substrate doping, flatband voltage and polysilicon doping (if applicable) can be extracted from C-V data, and potentially band offsets, dielectric constants and tunneling masses can be extracted from I-V data of single or multiplayer gate stacks.
Keywords :
MOS capacitors; annealing; capacitance; dielectric materials; leakage currents; permittivity; semiconductor doping; silicon; silicon compounds; MOS capacitors; SiO2-Si; SiO2-high-K gate dielectrics; annealing; dielectric constants; gate capacitance; gate leakage current; multiplayer gate stacks; polysilicon doping; surface substrate doping; tunneling masses; Capacitance; Capacitance-voltage characteristics; Data mining; Dielectric materials; Doping; High K dielectric materials; Leakage current; MOS capacitors; Nanoscale devices; Simulated annealing;
Conference_Titel :
University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial
Print_ISBN :
0-7803-7972-1
DOI :
10.1109/UGIM.2003.1225729
