DocumentCode :
1962448
Title :
Printable die attach adhesives for substrate-on-chip packaging
Author :
Becker, Kevin ; Lin, Timmy
Author_Institution :
Ablestik, Rancho Dominguez, CA, USA
fYear :
2003
fDate :
30 June-2 July 2003
Firstpage :
250
Lastpage :
255
Abstract :
The dominant trend in packaging DDR DRAM for the future is the face down substrate-on-chip configuration. For this type of package it is critical that the die attach method employed provide precise control of bond line thickness and die tilt, minimal fillet, and prevent contamination of the wire bond pads located on the edge of the center wire bond channel. To date, a film adhesive has been the die attach method of choice because it is well suited to meet those requirements. Unfortunately, films are quite expensive compared to die attach pastes in terms of material, process, and tooling costs. This is especially true when changes such as die shrinks and board redesigns mandate a taping tool change. To address this serious issue, a novel series of printable B-stage adhesives has been developed that deliver the performance of a film (with respect to bond line and flow control), with the low cost of a paste (in terms of tooling and materials).In this paper, we will present data on a commercial series and a developmental series of printable adhesives, which were developed specifically for substrate-on-chip packages. These proprietary adhesives are formulated to be stencil printed on a substrate and then B-staged. The printed substrates then replace the standard pre-taped substrates that represent the mainstream in DRAM packaging. Data show that these printable adhesives deliver the performance of films, i.e. low flow and bond-line control on die attach, more than a six month storage life at room temperature, and do not require substrate pre-drying. ChipMOS Technologies has pioneered the assembly process using these adhesives and are seeing high UPH and equivalent reliability performance to film adhesives. Key in-package reliability data from those evaluations will be presented.
Keywords :
CMOS integrated circuits; DRAM chips; adhesives; integrated circuit reliability; lead bonding; packaging; thin films; 293 to 298 K; DRAM; board redesigns; bond; bond-line control; chipMOS technologies; die tilt; film adhesive; printable die attach adhesives; reliability performance; room temperature; stencil printing; substrate-on-chip packaging; wire bond contamination; Bonding; Contamination; Costs; Microassembly; Packaging; Random access memory; Substrates; Temperature control; Thickness control; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial
ISSN :
0749-6877
Print_ISBN :
0-7803-7972-1
Type :
conf
DOI :
10.1109/UGIM.2003.1225737
Filename :
1225737
Link To Document :
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