An injection-locking based programmable fractional frequency divider with 0.2 division step for quantization noise reduction

A programmable fractional frequency divider with a division step size of 0.2 has been proposed in this paper. The circuit consists of a 5-stage ring oscillator which is injection locked to an external source. The different phases from the ring oscillator are linearly combined in a Phase Combiner (PC) based on the select signals produced by a state machine. These select signals are resynchronized with the phases to avoid glitches. This phase combined signal is then presented to a low-power dynamic divider set to division by an integer I. The result is a division by I.F where F is a multiple of the division step size 0.2. When used in a fractional-N PLL, this division step size reduction has the effect of reducing the quantization noise by 14 dB as compared to the case where a conventional multi-modulus divider (MMD) with division ratio step size of 1 is used.