A 0.3-to-8.5GHz frequency synthesizer based on digital period synthesis

Author

Rapinoja, Tapio ; Stadius, Kari ; Ryynanen, Jussi

Author_Institution

Dept. of Micro- & Nanosci., Aalto Univ., Espoo, Finland

fYear

2013

fDate

16-20 Sept. 2013

Firstpage

237

Lastpage

240

Abstract

This paper presents a wide-band digital frequency synthesizer based on digital period synthesis (DPS). As a direct frequency synthesis method, the DPS architecture achieves inherently wide operational band, high frequency resolution and instantaneous settling. The frequency synthesizer, including reference delay-locked loop (DLL), DPS unit, and frequency multiplying DLL, was implemented in a 65-nm CMOS process and it occupies an active area of 0.3 mm². The implemented frequency synthesizer covers a frequency range from 0.3 GHz to 8.5 GHz with 1 Hz frequency resolution, 550 fs integrated jitter, and 0.9 μs settling time.

Keywords

CMOS digital integrated circuits; UHF integrated circuits; direct digital synthesis; CMOS process; DPS architecture; DPS unit; digital period synthesis; direct frequency synthesis method; frequency 0.3 GHz to 8.5 GHz; frequency multiplying DLL; high frequency resolution; reference delay-locked loop; size 65 nm; time 0.9 mus; time 550 fs; wideband digital frequency synthesizer; Frequency synthesizers; Jitter; Phase locked loops; Phase noise; Synthesizers; Time-frequency analysis; Digital period synthesis; direct digital frequency synthesis; jitter; phase noise; settling time;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2013 Proceedings of the

Conference_Location

Bucharest

ISSN

1930-8833

Print_ISBN

978-1-4799-0643-7

Type

conf

DOI

10.1109/ESSCIRC.2013.6649116

Filename

6649116