Challenges in integration of Resonant Interband Tunnel Devices with CMOS

Author

Sudirgo, Stephen ; Curanovic, Branislav ; Rommel, Sean L. ; Hirschman, Karl D. ; Kurinec, Santosh K. ; Jin, Niu ; Rice, Anthony T. ; Berger, Paul R. ; Thompson, Phillip E.

Author_Institution

Dept. of Microelectron. Eng., Rochester Inst. of Technol., NY, USA

fYear

2003

fDate

30 June-2 July 2003

Firstpage

275

Lastpage

278

Abstract

The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (J_p) of 188 A/cm² whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with J_p of 278 A/cm². Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and J_p of 332 A/cm². The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.

Keywords

CMOS integrated circuits; Ge-Si alloys; current density; leakage currents; resonant tunnelling diodes; semiconductor materials; CMOS; Si; Si wafers; Si-Ge; SiGe resonant interband tunnel devices; blanket growth; peak current density; peak-valley current ratio; source/drain regions; CMOS process; CMOS technology; Fabrication; Germanium silicon alloys; Microelectronics; Resonance; Resonant tunneling devices; Semiconductor diodes; Silicon germanium; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

University/Government/Industry Microelectronics Symposium, 2003. Proceedings of the 15th Biennial

ISSN

0749-6877

Print_ISBN

0-7803-7972-1

Type

conf

DOI

10.1109/UGIM.2003.1225742

Filename

1225742