Challenges in integration of Resonant Interband Tunnel Devices with CMOS

The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (J_p) of 188 A/cm² whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with J_p of 278 A/cm². Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and J_p of 332 A/cm². The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.