Title :
A 0.4 GHz – 4 GHz direct RF-to-digital ΣΔ multi-mode receiver
Author :
Wu, Chunlin ; Nikolic, B.
Author_Institution :
EECS Dept., Univ. of California, Berkeley, Berkeley, CA, USA
Abstract :
A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A multi-level (two-bit) non-return-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier guarantees a highly linear front end. The peak SNDR of the receiver exceeds 68 dB for a 4 MHz signal, and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of +10 dBm and an IIP2 of +50 dBm is achieved while dissipating only 40 mW from 1.1 V / 1.5 V supply voltages.
Keywords :
CMOS digital integrated circuits; delta-sigma modulation; low-power electronics; operational amplifiers; radio receivers; tuning; CMOS; IIP2; IIP3; antenna; class-AB low-noise transconductance amplifier; direct RF-to-digital ΣΔ multimode receiver; frequency 0.4 GHz to 4 GHz; frequency 4 MHz; highly linear front end; jitter immunity; multilevel nonreturn-to-zero DAC; negative feedback digitizer; power 40 mW; size 65 nm; voltage 1.1 V to 1.5 V; wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture; Band-pass filters; Clocks; Jitter; Mixers; Optical signal processing; Receivers; Switches;
Conference_Titel :
ESSCIRC (ESSCIRC), 2013 Proceedings of the
Conference_Location :
Bucharest
Print_ISBN :
978-1-4799-0643-7
DOI :
10.1109/ESSCIRC.2013.6649126