Interfacial fracture mechanics: chip-level interconnect reliability

One of the most imposing challenges in developing semiconductor devices is understanding the interaction between their chip-level interconnect structures and the packaging materials that contact them. Structural integrity is a major reliability concern for high-density chip packages due to thermomechanical deformations and stresses. Semiconductor technology is moving toward replacing traditional Al/TEOS oxide interconnects with Cu damascene structures having oxide and low-k interlevel dielectrics. Compared to TEOS oxide, the low-k dielectric is softer, expands more rapidly, and is less adhesive to other materials, as shown in the results of the micromechanical testing, Moire interferometry, and finite element analysis (FEA) numerical simulation discussed in this paper.