Fault diagnosis of interconnection circuits in wafer scale arrays

An efficient diagnosis algorithm for data paths (or interconnection circuits) in reconfigurable arrays is proposed. The data paths, including data registers, data links, and programmable switches, are tested by applying test patterns from the outside of an array. Fault-free paths identified partition the array into smaller subarrays so that testing can be done recursively. Fault masking due to programmable switch failures is examined. A sufficient condition to avoid fault masking is obtained. The performance of the diagnosis algorithm is evaluated by computer simulation