Title :
Impact of partial reset on fault independent testing and BIST
Author :
Nguyen, Huy ; Roy, Rabindra ; Chatterjee, Abhijit
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Partial reset has been shown to have significant impact on deterministic test generation for sequential circuits. In this paper we explore the use of partial reset in fault-independent testing and application to built-in self-test. We take the following approach: based on fault propagation analysis, we select a subset of the circuit flip-flops to be initialized to 0 or 1. The initialization (set/reset) is performed periodically while the test input vectors to the sequential circuit are applied. An average improvement of 15% in fault-coverage has been obtained for circuits resistant to random pattern testing
Keywords :
VLSI; automatic testing; built-in self test; fault diagnosis; flip-flops; integrated circuit testing; logic testing; sequential circuits; BIST; circuit flip-flops; deterministic test generation; fault independent testing; fault propagation analysis; partial reset; random pattern testing; sequential circuits; test input vectors; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Flip-flops; Performance evaluation; Sequential analysis; Sequential circuits; Test pattern generators;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568202
