Title :
A framework for testing stuck-open fault in CMOS LSI/VLSI circuits
Author :
Abuelyaman, Eltayeb S. ; Hedroug, Nacer E.
Author_Institution :
Dept. of Electr. Eng., Western Michigan Univ., Kalamazoo, MI, USA
Abstract :
A conceptual framework for modeling of CMOS stuck-open faults by classical stuck-at faults is presented. Stuck-open faults can be mapped one-to-one onto stuck-at faults for a gate level, clock-mode fault simulation. The disadvantage of this modeling is that it restricts the circuit layout to logic gates, and hence an increase in chip area is expected. Such an increase is acceptable when the modeling reduces the staggering fault simulation time by a large factor
Keywords :
CMOS integrated circuits; VLSI; fault location; integrated logic circuits; large scale integration; logic testing; CMOS; LSI; VLSI; chip area; circuit layout; clock-mode fault simulation; conceptual framework; gate level; staggering fault simulation time; stuck-at faults; stuck-open fault; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Clocks; Large scale integration; Logic circuits; Logic gates; Semiconductor device modeling; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101853
