On multiple fault analysis in synchronous sequential circuits by Boolean difference techniques

A vector Boolean difference technique is used in the synthesis of test sequences for synchronous sequential circuits. The technique determines the set of input/state pairs that will produce a difference in output between a faulty and fault-free circuit. A method for deriving the required shortest test sequence to detect a specified multiple fault in which transition tables of fault-free and faulty circuits are combined to form a detecting tree is discussed. The technique is quite straightforward, and has already been implemented in C programming language to run in a mainframe computer for testing simple ICs