DocumentCode :
1963520
Title :
On incorporation of BIST for the synthesis of easily and fully testable controllers
Author :
Mitra, S. ; Mohan, C. Rama ; Chaudhuri, P. Pal
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
fYear :
1997
fDate :
4-7 Jan 1997
Firstpage :
547
Lastpage :
562
Abstract :
BIST (Built-In-Self-Test) has received significant attention in, both academic and industrial circles, as id offers solutions to several major testing problems at both chip level as well as system level. However most of the commercial RTL synthesis tools to date, used by designers offer full scan and/or partial scan solutions for testing the synthesized netlists thus making the effectiveness of the testing scheme totally governed by the effectiveness of ATPGs in generating the necessary test patterns to ensure high testability. Designing a sequential ATPG to ensure high testability of FSMs in all types of RTL designs is a complex task. In this work, we have proposed a Cellular Automata (CA) based BIST scheme for testing FSMs in the netlists generated after synthesizing a VERILOG/VHDL description. The scheme makes the FSMs fully testable for a single stuck-at fault model. We have integrated this scheme for testing control part into SYNERGY which is the Cadence RTL synthesis tool. The generated netlists have been simulated using VERILOG simulator of Cadence for verifying the functional correctness. The experimental results on a typical target library have shown a BIST area overhead of around 10% in most of the designs and 13% and 17% in two designs
Keywords :
VLSI; automatic testing; built-in self test; cellular automata; finite state machines; hardware description languages; integrated circuit testing; logic testing; sequential circuits; ATPGs; BIST; Cadence; FSMs; RTL designs; SYNERGY; VERILOG; VHDL; area overhead; cellular automata; full scan; fully testable controllers; partial scan; stuck-at fault model; target library; testability; testing scheme; Automatic testing; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Design for testability; Hardware design languages; Logic testing; Sequential analysis; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
ISSN :
1063-9667
Print_ISBN :
0-8186-7755-4
Type :
conf
DOI :
10.1109/ICVD.1997.568207
Filename :
568207
Link To Document :
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