Negative bias instability in silicon-on-sapphire n-channel MOSFETs

Author

Do, N.T. ; Vu, T.Q. ; Warren, G. ; Li, G.P. ; Tsai, C.S.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

fYear

1998

fDate

5-8 Oct. 1998

Firstpage

85

Lastpage

86

Abstract

Summary form only given. This paper reports detailed measurements of device degradation in silicon-on-sapphire (SOS) multi-edge n-channel MOSFETs (NMOS) caused by a negative bias-temperature (NET) stress on the gate. The stressed NMOS devices exhibit a negative shift in the threshold voltage, V/sub th/, and an increase in leakage current, I/sub lk/. In contrast, edgeless NMOS devices show no significant changes in their voltage and current characteristics. It is therefore believed that the degradation in the multi-edge NMOS devices is caused by a threshold voltage shift in the edge transistor.

Keywords

MOSFET; leakage currents; semiconductor device measurement; semiconductor device reliability; silicon-on-insulator; stability; thermal stresses; SOS multi-edge n-channel MOSFETs; Si-Al/sub 2/O/sub 3/; current characteristics; device degradation measurements; edge transistor threshold voltage shift; edgeless NMOS devices; leakage current; multi-edge NMOS device degradation; negative bias instability; negative bias-temperature gate stress; negative threshold voltage shift; silicon-on-sapphire n-channel MOSFETs; stressed NMOS devices; voltage characteristics; Degradation; MOS devices; MOSFETs; Pollution measurement; Silicon; Stress measurement; Substrates; Subthreshold current; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1998. Proceedings., 1998 IEEE International

Conference_Location

Stuart, FL, USA

ISSN

1078-621X

Print_ISBN

0-7803-4500-2

Type

conf

DOI

10.1109/SOI.1998.723123

Filename

723123