Title :
A new CMOS gate-the balanced gate-for detecting physical failures
Author :
Katter, Orlando E., Jr. ; Razavi, Hassan M.
Author_Institution :
Winthrop Coll., Rock Hill, SC, USA
Abstract :
An approach to design-for-testability of CMOS logic circuits is presented. The method is based on design with a new family of gates, called balanced gates. These gates have an extra logic level that is used for testing. In the test mode, all the inputs to a gate are at 2.5 V, and if there are no faults the output would be at 2.5 V (gate is balanced). Circuits made with this family of gates require one test vector (2.5 V for each input) to achieve an acceptable level of fault detection. Simulation results indicate that circuits made from balanced gates are easily testable
Keywords :
CMOS integrated circuits; integrated logic circuits; logic design; logic testing; CMOS logic circuits; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Educational institutions; Electrical fault detection; Logic design; Logic testing; Sequential circuits; Very large scale integration;
Conference_Titel :
Multiple-Valued Logic, 1990., Proceedings of the Twentieth International Symposium on
Conference_Location :
Charlotte, NC
Print_ISBN :
0-8186-2046-3
DOI :
10.1109/ISMVL.1990.122588
