• DocumentCode
    1963681
  • Title

    Investigation of a lead-free flip chip assembly process

  • Author

    Kums, G. ; Duan, N. ; Scheer, J. ; van Kleef, M. ; Wijers, J. ; Bielen, J.

  • Author_Institution
    Philips Centre for Ind. Technol., Eindhoven, Netherlands
  • fYear
    2003
  • fDate
    16-18 July 2003
  • Firstpage
    93
  • Lastpage
    98
  • Abstract
    The integration of passive components into a single chip was developed to meet the increasing demands on cost and size reduction of the current RF power amplifier modules. Flip chip assembly on a laminate substrate using lead-free solder bumps was used for the module level assembly. In this paper, the detailed investigation of the assembly process is reported. This includes, among others, solder paste printing, flip chip placement and underfill application. The challenge of this flip chip assembly was the lead-free processing in both first level and second level interconnects and the required short throughput time from the pre-development to the mass production in the factory. First an orientation study was performed to find an optimum process window and two potential underfill candidates. Samples were made with the optimum process setting. To verify the process feasibility, thermal shock testing, moisture sensitivity assessment and high temperature storage testing were carried out. The reliability test results showed that one type of underfill performed very well, while another one could not meet the reliability requirements. The root failure cause with the troublesome underfill was found not to be caused by the assembly process but to be related to the underfill material and the via construction in the substrate.
  • Keywords
    flip-chip devices; mass production; microassembling; power amplifiers; reliability; semiconductor device packaging; sensitivity; soldering; thermal shock; assembly process; cost; current RF power amplifier modules; demands; flip chip assembly process; flip chip placement; high temperature storage testing; laminate substrate; lead free processing; lead-free solder bumps; mass production; module level assembly; moisture sensitivity assessment; optimum process setting; optimum process window; passive component integration; process feasibility; reliability test; size reduction; solder paste printing; thermal shock testing; Assembly; Costs; Environmentally friendly manufacturing techniques; Flip chip; Laminates; Lead; Power amplifiers; Radio frequency; Radiofrequency amplifiers; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. IEEE/CPMT/SEMI 28th International
  • ISSN
    1089-8190
  • Print_ISBN
    0-7803-7933-0
  • Type

    conf

  • DOI
    10.1109/IEMT.2003.1225884
  • Filename
    1225884