Title :
Dynamically configurable combinatory logic array as Boolean neural network
Author :
Niittylahti, Jarkko ; Raittinen, Harri ; Kaski, Kimmo
Author_Institution :
SEFT, CERN, Geneva, Switzerland
Abstract :
A dynamically configurable combinatory logic array has been developed to be used as a Boolean neural network. The dynamical configuration facility enables hardware training using the simulated annealing method. The system is capable of adapting to a binary mapping task on the basis of given examples. The design target has been a cascadable VLSI chip
Keywords :
VLSI; cascade networks; combinational circuits; feedforward neural nets; integrated logic circuits; learning systems; logic arrays; neural chips; neural net architecture; reconfigurable architectures; simulated annealing; Boolean neural network; binary mapping task; cascadable VLSI chip; dynamically configurable combinatory logic array; hardware training; simulated annealing method; Boolean functions; Hardware; Logic arrays; Logic gates; Multi-layer neural network; Multiplexing; Neural networks; Switches; Temperature; Very large scale integration;
Conference_Titel :
Tools with Artificial Intelligence, 1993. TAI '93. Proceedings., Fifth International Conference on
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-4200-9
DOI :
10.1109/TAI.1993.634000
