DocumentCode :
1963940
Title :
A 3–10fJ/conv-step 0.0032mm2 error-shaping alias-free asynchronous ADC
Author :
Patil, Sharvil ; Ratiu, Alin ; Morche, Dominique ; Tsividis, Yannis
Author_Institution :
Columbia Univ., New York, NY, USA
fYear :
2015
fDate :
17-19 June 2015
Abstract :
We present a programmable, quantization error spectral shaping, alias-free asynchronous ADC suited for clockless, continuous-time DSP in receivers with modest SNDR requirements and a tight power budget. Implemented in 0.65V 28nm FDSOI, the 0.0032mm2 ADC achieves 32dB-42dB SNDR over a 10MHz-50MHz BW while consuming 24μW, giving a 3-10fJ/conv-step FoM.
Keywords :
analogue-digital conversion; asynchronous circuits; digital signal processing chips; silicon-on-insulator; FDSOI; SNDR; analog-digital converter; bandwidth 10 MHz to 50 MHz; continuous-time DSP; digital signal processor; error-shaping alias-free asynchronous ADC; fully depleted silicon-on-insulator; power 24 muW; power budget; quantization error spectral shaping; size 28 nm; voltage 65 V; Clocks; Digital signal processing; Modulation; Power dissipation; Quantization (signal); Receivers; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
Type :
conf
DOI :
10.1109/VLSIC.2015.7231249
Filename :
7231249
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1963940
بازگشت