Title :
Backend processing for wafer level chip scale packaging
Author_Institution :
Adv. Semicond. Eng., Inc., Tempe, AZ, USA
Abstract :
As the electronics industry has continued its pursuit of miniaturization at the IC, package, card and system levels; high-density packaging technologies have been developing at an ever increasing rate to provide these smaller, lighter, faster, and cheaper packages and sub-systems. To achieve this greater functionality per unit volume for portable and miniature electronic assemblies, Wafer Level Chip Scale Packaging (WLCSP) has become an important packaging alternative for the electronics industry. Within the next year, volumes of WLCSP product are expected to increase more than twofold. As WLCSPs are limited to relatively small die, the number of die per 200 mm wafer can range from 2 K die per wafer to over 20 K die per wafer. This creates the requirement for the backend processing of extremely high volumes of WLCSP die. The processes and equipment have had to evolve rapidly in order to accommodate the processing and inspection of these large volumes of WLCSP die product.
Keywords :
chip scale packaging; electronics industry; microassembling; semiconductor technology; wafer bonding; IC miniaturization; WLCSP die product; backend processing; card miniaturization; density packaging technologies; electronics industry; miniature electronic assemblies; package miniaturization; system level miniaturization; wafer level chip scale packaging; Assembly; Chip scale packaging; Electronics industry; Electronics packaging; Integrated circuit packaging; Logic devices; Manufacturing processes; Printing; Semiconductor device packaging; Wafer scale integration;
Conference_Titel :
Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. IEEE/CPMT/SEMI 28th International
Print_ISBN :
0-7803-7933-0
DOI :
10.1109/IEMT.2003.1225897