DocumentCode
1963952
Title
The Design of HDTV H.264 Encoding System Based on Multi-DSPs Architecture
Author
Wang, Jintao ; Lv, Rui ; Gao, Pengdong ; Lu, Yongquan ; Qiu, Chu ; Yu, Wenhua
Author_Institution
Commun. Univ. of China, Beijing
Volume
4
fYear
2008
fDate
12-14 Dec. 2008
Firstpage
54
Lastpage
57
Abstract
The emerging coding standard H.264 is mainly intended for video transmission in many areas. Considering the peculiarity of High-Definition TV (HDTV) encoding, the fast development of parallel technology and high-speed DSPs, the efficient hardware architectures were researched for the algorithm of H.264 encoding. After analyzing the experiment results from different platforms, we discussed the application method and the principle of picture splitting as parallel granularity. The parallel system structure based on multi-DSPs, which has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility, adopted frame-level load grain, was designed.
Keywords
data compression; digital signal processing chips; high definition television; logic design; parallel algorithms; video coding; HDTV H.264 encoding system design; High-Definition TV encoding; adopted frame-level load grain; broad I/O bandwidth; code standard H.264; high-speed multiDSPs architecture; parallel algorithm; parallel system structure; topology flexibility; video transmission; Computer architecture; Digital signal processing; Encoding; HDTV; High definition video; ISO standards; Parallel algorithms; Real time systems; Standards development; Video coding; High-Definition TV; Operation Block; Pipeline; multi-DSPs; parallel algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Science and Software Engineering, 2008 International Conference on
Conference_Location
Wuhan, Hubei
Print_ISBN
978-0-7695-3336-0
Type
conf
DOI
10.1109/CSSE.2008.517
Filename
4722562
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