A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture

Author

Sang Min Lee ; Dongwon Seo ; Taleie, Shahin Mehdizad ; Derui Kong ; McGowan, Michael Joseph ; Tongyu Song ; Saripalli, Ganesh ; Kuo, Jenny ; Bazarjani, Seyfi

Author_Institution

Qualcomm Technol., Inc., San Diego, CA, USA

fYear

2015

fDate

17-19 June 2015

Abstract

A 14b 750MS/s 21.1mW current steering digital-to-analog converter (DAC) is presented, which maintains <;-168dBm/Hz noise spectral density beyond the Nyquist frequency to minimize TX leakage in SAW-less FDD LTE. A hybrid wideband R-2R LSB segmentation with an impedance attenuator minimizes glitch noise across process and temperature without requiring accurate scaling of switches and switch drivers. SFDR of 79dBc is achieved at 15MHz with a distortion cancellation circuit. The DAC occupies 0.47mm² in a 20nm CMOS process with an on-chip calibration engine which guarantees 14b monotonicity.

Keywords

CMOS analogue integrated circuits; digital-analogue conversion; integrated circuit noise; CMOS integrated circuit; beyond Nyquist noise floor; current steering DAC; digital-analog converter; low glitch noise hybrid R-2R architecture; on-chip calibration engine; size 20 nm; CMOS integrated circuits; Capacitors; Frequency measurement; Impedance; Noise; Nonlinear distortion; 20nm; CMOS; DAC; R-2R; glitch noise; negative resistance; process and temperature variation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSI Circuits), 2015 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-86348-502-0

Type

conf

DOI

10.1109/VLSIC.2015.7231251

Filename

7231251