• DocumentCode
    1964116
  • Title

    A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay

  • Author

    Singh, Vikas ; Krishnapura, Nagendra ; Pavan, Shanthi ; Vigraham, Baradwaj ; Nigania, Nimit ; Behera, Debasish

  • Author_Institution
    Dept. of Electr. Eng., Indian Inst. of Technol., Chennai, India
  • fYear
    2011
  • fDate
    19-21 Sept. 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    An 800MS/s CT ΔΣ ADC with 16MHz/32MHz bandwidths consumes 47.6mW from 1.8V and occupies 1mm2 in a 0.18μm CMOS process. The DR/SNR/SNDR for the two bandwidths are 75/67/65 dB and 64/57/57 dB respectively. Excess loop delay (ELD) of more than one cycle is compensated using a fast path outside the flash ADC. This and a low latency flash ADC and delay free DAC calibration result in the highest reported sampling rate in this process.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; CMOS process; bandwidth 16 MHz; bandwidth 32 MHz; delay free DAC calibration; delta-sigma ADC; excess loop delay; low latency flash ADC calibration; power 47.6 mW; size 0.18 mum; voltage 1.8 V; Ash; Bandwidth; Calibration; Delay; Feedforward neural networks; Modulation; Noise;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2011 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4577-0222-8
  • Type

    conf

  • DOI
    10.1109/CICC.2011.6055291
  • Filename
    6055291
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1964116