• DocumentCode
    1964238
  • Title

    ReSSP: A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor

  • Author

    Chan, Wei-Kai ; Tseng, Yu-Hsiang ; Tsung, Pei-Kuei ; Chuang, Tzu-Der ; Tsai, Yi-Min ; Chen, Wei-Yin ; Chen, Liang-Gee ; Chien, Shao-Yi

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2011
  • fDate
    19-21 Sept. 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A 5.877 TOPS/W Reconfigurable Smart-camera Stream Processor is implemented in 90nm CMOS technology. A reconfigurable hardware architecture with heterogeneous stream processing and subword-level parallelism is implemented to accelerate the vision processing for smart-camera applications. The area efficiency reaches 111.329 GOPS/mm2. The power efficiency and area efficiency are 4.5× to 33.0× and 3.8× to 74.2× better than the state-of-the-art works, respectively.
  • Keywords
    CMOS integrated circuits; cameras; microprocessor chips; parallel processing; reconfigurable architectures; CMOS technology; ReSSP; TOPS/W reconfigurable smart-camera stream processor; heterogeneous stream processing; reconfigurable hardware architecture; size 90 nm; subword-level parallelism; vision processing; Hardware; Logic gates; Memory management; Silicon; Streaming media; System-on-a-chip; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2011 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4577-0222-8
  • Type

    conf

  • DOI
    10.1109/CICC.2011.6055296
  • Filename
    6055296
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1964238