Generation of Executable Representation for Processor Simulation with Dynamic Translation

Instruction-Set Simulators (ISS) are indispensable tools for studying new architectures. There are several alternatives to achieve instruction set simulation, such as interpretive simulation, static translation and dynamic translation. This paper presents a simulator where we have developed and integrated three techniques: an interpretive simulator and two variants of dynamic translation. In the third variant,the simulator caches an intermediate representation that consists of pseudo instructions. These pseudo instructions use semantic functions that can be specialized using partial evaluation technique and a code generator. These three methods have been used to run the same simulated programs and compare their performance. The experiments show that the partial evaluation technique increases performance and flexibility, but also shows that it may have adverse effects.