• DocumentCode
    1964370
  • Title

    Board level reliability evaluation of RF PA module vias

  • Author

    Darveaux, Robert ; Yang, Jicheng ; Syed, Ahmer ; Buella, Boy ; Villareal, Paul ; Kang, W.J.

  • Author_Institution
    Amkor Technol., Inc., Chandler, AZ, USA
  • fYear
    2003
  • fDate
    16-18 July 2003
  • Firstpage
    305
  • Lastpage
    311
  • Abstract
    The reliability of RF PA module substrate vias was evaluated using nine different laminate constructions. Variables in the substrate construction included layer count, trace thickness, via wall thickness, via diameter, via plugging, via capping, core material, and process flow at the supplier. A daisy chain module was designed to simulate a typical over molded RF PA module. The body size was 10×10 mm, with 2 die, 20 components, and 34 LGA I/O pads. Daisy chain nets were formed through 2 via chains, and 1 SMD component chain. Via reliability was measured by temperature cycling at -55°C <=> 125°C, 2 cph, after pre-conditioning at Jedec L3/240°C and L3/260°C. Both package level and board level testing was conducted. In the package level tests, it was found that nearly all of the constructions passed the typical qualification requirement of 1000 temperature cycles. However, one construction had failures starting at 600 cycles due to cracks in the knee region of the substrate vias. This construction used a less robust manufacturing flow at the substrate supplier. Three of the nine constructions were evaluated in the board level tests. All three legs passed the 1000 temperature cycle requirement, with the first via failure observed at 1372 cycles. No 2nd level solder joint failures were observed before the test was terminated at 3779 cycles. This robust board level temperature cycling performance is due to large NSMD pads (0.8 mm×0.8 mm), and small die (1.0 mm×1.0 mm). Failure analysis was conducted on all test legs to understand crack initiation sites and crack growth paths in the substrate vias.
  • Keywords
    chip-on-board packaging; curing; electronics packaging; failure analysis; integrated circuit manufacture; integrated circuit reliability; integrated circuit testing; laminates; printed circuits; reflow soldering; substrates; surface cracks; surface mount technology; -55 to 125 degC; 0.8 to 0.8 mm; 1.0 to 1.0 mm; 10 to 10 mm; 240 to 260 degC; board level testing; capping; core material; crack growth paths; crack initiation sites; daisy chain module; failure analysis; laminate constructions; layer count; module substrate vias; package level testing; plugging; printed circuit board; process flow; reliability evaluation; solder joint failures; substrate construction; temperature cycling; trace thickness; Building materials; Laminates; Leg; Modular construction; Packaging; Qualifications; Radio frequency; Robustness; Temperature measurement; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. IEEE/CPMT/SEMI 28th International
  • ISSN
    1089-8190
  • Print_ISBN
    0-7803-7933-0
  • Type

    conf

  • DOI
    10.1109/IEMT.2003.1225918
  • Filename
    1225918